1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and more particularly, to a method for forming a self-aligned buried contact hole which can increase the contact margin between a gate electrode and a pad electrode.
2. Description of Related Art
For highly integrated semiconductor devices, such as DRAMs, knowledge of insulating film material properties, lithography, cell structure and new wiring materials is required. In a 64 Mega-bit DRAM, the contact hole area must be reduced according to the reduction of the cell size.
A typical 64 Mega-bit DRAM device has a design rule of approximately 0.3 .mu.m to 0.4 .mu.m, even though the contact hole is formed into the general feature size, i.e., 0.5 .mu.m. The peripheral structure, that is, a gate electrode or a bit line, is frequently exposed as a result of a mis-aligned mask. As a result, the gate electrode contacts a storage electrode and a bit line contacts a storage electrode contact, which greatly reduces the reliability of the DRAM.
Several methods have been proposed for reliably minimizing contact hole area without exposing the peripheral structure caused by a mis-aligned mask. One such method calls for forming a self-aligned contact hole.
In a method for forming a self-aligned contact hole, a step of forming the peripheral structure is used to obtain a contact hole without using a mask. The hole size depends on the height of the peripheral structure, thickness of the insulating material where the contact hole is formed, and the etching method. Therefore, forming a self-aligned contact hole is a method suitable for realizing a highly-integrated semiconductor device.
In general, the gate electrodes of the semiconductor device consist of a gate oxide film, polycrystalline silicon and high temperature oxide film. In order to form a self-aligned contact hole, capping oxide film having sufficient thickness is deposited to complement the etching margin when the contact hole is formed in the edge portion of the gate electrode. Thus, a high-step gate electrode can be produced.
FIG. 1 shows an embodiment of a contact hole of the conventional semiconductor memory device formed by the self-aligned method described above. Gate oxide film 11 is formed on a semiconductor substrate 100. Then, a polycrystalline silicon 12 and an insulating oxide film 13 are deposited, and a gate electrode 101(12, 13) is formed by a photo-etching process. Then, a high temperature oxide film 14 is deposited all over the substrate. A photoresist 15 is deposited and a self-aligned buried contact hole is formed by a photo-etching process. Accordingly, when the thickness of oxide films 13 and 14 deposited all over the gate electrode is not sufficient, the edge of the gate electrode is etched faster than the etching for forming the contact hole is performed. As a result, the edge of the gate electrode is exposed inside of the contact hole.
FIG. 2 shows another embodiment of a contact hole of the conventional semiconductor memory device formed by a self-aligned method described above. A gate oxide film 21 is formed on a semiconductor substrate 200. Then, a polycrystalline silicon 22 and a capping oxide film (insulating oxide film) 23 are deposited, and capping oxide film 23 is etched by a photo-etching process. Polycrystalline silicon 22 is isotropically etched, to thereby form a gate electrode 201 (22, 23). A high temperature oxide film 24 is deposited all over the substrate and a photoresist 25 is deposited. Then, a self-aligned buried contact hole is formed by a photo-etching process. Controlling the hole size is difficult when polycrystalline silicon 22 is isotropically etched, and the surface resistance of polycrystalline silicon 22 is increased. As a result, it is difficult to achieve a highly integrated semiconductor device using this method.